Design Verification Intern
- Design of Digital circuits using Verilog & System Verilog HDL.
- Verification of Digital circuits using System Verilog with UVM Methodology
- Simulation of digital circuits using Modelsim simulation environment.
- Also assist with creating technical documentation for products developed.
- User level Linux operating system knowledge
- 4th year student in Electronics and Telecommunication, Automatics or Electrical Faculty
- Basic knowledge of microprocessor architecture and digital circuits
- Good knowledge of English and good communications skills
- Mentor & Cadence tools experience is a plus.
- Learn quickly and able to be in the right gear all the time