Design team member who is an active participant in layout design of analog , mixed signals or digital blocks;
Perform layout of CMOS analog /mixed signals circuits using Cadence tools;
Perform verification of layout adherence to design rules (DRC) and Layout-vs-Schematic checks
3rd / 4th year student or MSEE in Electronics and Telecommunication or Electrical Faculty
Knowledgeable of basic analog and digital circuits.
CMOS technology knowledge is a plus.
Experience in layout of CMOS analog circuits is a plus;
Should have good knowledge of English and good communication skills