DFT Architect/Lead Engineer - Test

Cork, IE

Req ID: I909-19

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Company Description

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.

Job Description

Microchip’s fast-growing Analog Power and Interface Division (APID) is looking for an experienced, innovative and passionate Design-For-Test (DFT) Architect/Lead Engineer to join our talented test architecture team in our new Design Centre in Cork.  In this role you will have the opportunity to define and implement DFT best practices to help make designs easier to test, more cost effective and provide reusable building blocks that can be used for multiple semiconductor device test applications. As a senior technical member of the test development team, you will also be responsible to help coach, mentor and train junior test engineering staff and actively participate in the development of key test strategic decisions.

Key Responsibilities:

  • To perform detailed reviews of design specifications and evaluate/define design for testability (DFT) features.
  • Utilize experience in DFT implementation for analog and digital testing methodologies.
  • Provide technical leadership for developing DFT architectures.
  • Proactively participate as a member of the project team starting from early project definition phase until release to production.
  • Define DFT requirements and write detailed DFT manuals to be used by design and test teams.
  • Apply knowledge of ATE tester instruments and ATE board limitations.
  • Work in partnership with various product line teams including design, test, validation, applications, and product engineering.
  • Collaborate with worldwide cross-functional project teams.
  • To take on people management, coaching and mentoring responsibilities as the team expands  

Job Requirements

Key Job Requirements

  • A university degree in Electronics or Computer Engineering with 10+ years of experience within the semiconductor industry.
  • Analog design experience required for close development of DFT IP blocks.
  • Experience in mentoring junior engineers and staff.
  • Experience with ATE requirements and testers.
  • Understand block diagrams of analog building blocks to analyze DFT needs.
  • Understand device behavior and modes in terms of observability and controllability using different test conditions and possible impact on ATE tests.
  • Must possess excellent communication skills and ability to work in a global multi-functional team environment.
  • Strong team player and open minded.

Desirable Skills & Experience

  • Experience of analog and mixed-signal ATE platforms.
  • Understanding of SCAN, IDDQ, BIST, statistical process control, calibration theory, and test limit guard banding methodology.
  • Experience of Conducting comprehensive Test Plan Reviews and Peer Reviews.
  • Experience leading a small test team or directly responsible for the coaching or mentoring of junior staff.


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