Principal Engineer - Analog Design for Test (DFT)

Cork, IE

Req ID: I909-19

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Company Description

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.

Job Description

Microchip’s fast-growing Analog Power and Interface Division (APID) is looking for an experienced, and innovative Principal Engineer with knowledge in Analog/Mixed-Signal design who wants to work on DFT requirements and definitions for analog and digital blocks. In this role you will have the opportunity to work close with the design team, to analyze block diagrams and device specifications against testability of device parameters and functionality. As a senior technical member of the test development team,  you will actively participate in the development of key decisions around our test strategy. As the role develops in the future you may also have the opportunity to lead, coach, mentor, or train junior test engineering staff.

Key Responsibilities:

  • To perform detailed reviews of design specifications and evaluate/define design for testability (DFT) features.
  • Utilize experience in DFT implementation for analog and digital testing methodologies.
  • Provide technical leadership for developing DFT architectures.
  • Proactively participate as a member of the project team starting from early project definition phase until release to production.
  • Define DFT requirements and write detailed DFT manuals to be used by design and test teams.
  • Apply knowledge of ATE tester instruments and ATE board limitations.
  • Work in partnership with various product line teams including design, test, validation, applications, and product engineering.
  • Collaborate with worldwide cross-functional project teams


Job Requirements

We are looking for candidates that are self-driven, motivated, and capable of embracing a fast paced, environment focused on continuously innovation and efficiency.  From a technical perspective candidates should have experience in all stages of new product test development and DFT methodologies are critical to this position.  The ideal candidate should not only have excellent technical skills but also be an effective communicator, with the ability to influence others and be an effective team player working effectively with the various stakeholder across the business.  We work as part of a global cross functional team focused on contributing, informing, influencing, and supporting the development of shared test applications within Microchip.

Required Technical and Professional Expertise

  • A university degree in Electronics or Computer Engineering with 10+ years of experience within the semiconductor industry.
  • Analog design experience required for close development of DFT IP blocks.
  • Understand block diagrams of analog building blocks to analyze DFT needs.
  • Understand device behavior and modes in terms of observability and controllability using different test conditions and possible impact on ATE tests.
  • Must possess excellent communication skills and ability to work in a global multi-functional team environment.
  • Strong team player and open minded.

Desirable Technical and Professional Experience

  • Experience of analog and mixed-signal ATE platforms.
  • Understanding of SCAN, IDDQ, BIST, statistical process control, calibration theory, and test limit guard banding methodology.
  • Experience of conducting comprehensive test plan reviews and peer reviews.
  • Have the potential to grow in the role and to lead a small test team or to provide coaching or mentoring to junior engineers.


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