Senior Engineer II - Implementation

Bangalore, IN

Req ID: I779-20AB

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Company Description

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.

Job Description

  • Develop and execute implementation plans to synthesize, implement Design For Test, and close timing on complex digital integrated circuits at the block, subsystem or chip level, which are coded in VHDL/Verilog. 
  • Use metric-driven techniques to help ensure first-pass working silicon.
  • Design, implement and maintain synthesis, DFT and Static Timing scripts using best-in-class methodologies. 
  • Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones.
  • Mentor Junior team members and contractor on implementation flows and projects.
  • Communicate regularly with the project teams world-wide to resolve issues, communicate status and solve technical problems. 

Job Requirements

This position requires at least B.E/B.Tech in Electronics with 7+ years of ASIC development experience in a fast paced environment with following experience.

  • Synthesis & STA experience in high performance design (high speed / low power) is a must.
  • Experience with tools and methodologies for Synthesis - hierarchical synthesis, DFT handling, retiming, clock gating, logic restructuring, optimization.
  • Experience in synthesis, low-power and high-speed design trade-offs, 'physical aware' synthesis, deep sub-micron process effects.
  • Experience in closing timing on block level and chip level in a highly complex clocking environment.
  • Good scripting skills; knowledge of synthesis & timing closure.
  • Backgrounds on standard cell, layout, timing/power views, and characterization would be added advantage.
  • Must be able to work autonomously.
  • Excellent oral and written communications skills.
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