Senior Engineer II - Digital Design

Bangalore, IN

Req ID: S209-20.3

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Company Description

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.

Job Description

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products

RTL Digital Design Engineer

The Mixed Signal Development Group (MSDG) looking to grow our design group within Microchip’s Penang facilities. We are seeking an individual with RTL design or verification experience to expand this group and build advanced high-speed SERDES and PHY designs in FinFET technologies.

Responsibilities:

  • Design and verification of RTL blocks for MSDG IP. This includes (but is not limited to) the following tasks:

    • Block specification & microarchitecture

    • RTL coding

    • Synthesis trials

    • Support SOC design teams to integrate MSDG IP.

    • Support of back-end engineers (synthesis, STA, layout)

    • Support of lab engineers

    • Documentation

  • Integrate analog IP into RTL designs to generate Mixed Signal IP subsystems.

  • Interact with other groups within the company: Validation, Production, FW, Product Development, Applications.

  • Perform digital simulations to qualify the RTL being developed.

  • Writing block level Verilog/System-Verilog directed test-benches and supporting verification team with debug.

Job Requirements

 

Qualifications:

  • Bachelor's or higher degree in Electrical Engineering.
  • Work experience: 2-5+ years of mixed signal ASIC development experience

  • Conversant with Synopsys liberto (.lib) cell characterization format.

  • Previous experience in writing/implementing/reviewing test plans.

  • Experience in automation and scripting with languages such as Python/Perl/TCL/Shell

  • Strong working knowledge of Verilog, SystemVerilog, and VerilogA.

  • Experience with all phases of ASIC design (RTL, verification, synthesis, layout, etc)

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