Senior Physical Design Engineer-I

Bangalore, IN

Req ID: I512-22A-E

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Company Description

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.

Job Description

Skandysys Contractor conversion to Full Time Employees.

1

Praveen

B.E

4

Skandysys

Sr.Eng-I

IG

59

2

 

B.E

4.3

Skandysys

Sr.Eng-I

IG

59

3

 

B.E

4.3

Skandysys

Sr.Eng-I

IG

59

4

Prashanth M

B.E

4.6

Skandysys

Sr.Eng-I

ICPD

59

5

Shruthi V

B.E

6.5

Skandysys

Sr.Eng-II

ICPD

60

Job Requirements

About the Job:

Division: AES Implementation Team

Location: Chennai, India

 

Senior Design Implementation Engineer - I

The AES Implementation team is responsible for creating the design of a device by providing technical expertise through cutting edge design tools and technology. This team works closely with various business unit product development teams to ensure the design is physically realizable.

As a Design Implementation engineer, the candidate will be mentored by the team, be engaged into projects to perform the synthesis, DFT implementation, place and route, timing closure and ensure the design is implemented correctly with various checks/verification/audit. Also, be involved in design flow/methodology definition and development to ensure the design team is always using best-in-class design methodology.

Responsibilities:

  • Perform physical design flows, Place & Route and close timing on very large and complex ASICs and SOCs in Very-Deep Sub-Micron (VDSM) process technology nodes
  • sPerform synthesize, implement Design-For-Test (DFT) and close timing on complex digital integrated circuits at the block, subsystem or device level (100K to 10M+ gates) which are coded in VHDL/Verilog.
  • Work with project leaders to meet timing closure, area, power, and performance requirements for macro under development.
  • Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones.
  • Work closely with the Synthesis, DFT and local project lead to deliver blocks in hierarchical chips for tapeout in a timely, high quality and cost-effective manner
  • Potentially work on multiple blocks in parallel towards P&R/STA/DRC-LVS and IR Drop closure
  • Communicate regularly with the local project lead to resolve issues and to ensure meeting targeted goals and schedule.

Qualifications:

3+ years of experience in Physical Design.

            Education:

Masters/Bachelor’s Degree in Electrical / Electronics Engineering.

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