Engineer II - Systems Validation

San Jose, US

Req ID: NCG115-22

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Company Description

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.

Job Description

Microchip has been consistently recognized as one of the best places to work by prestigious publications like Forbes, Bay Area News and Phoenix Business Journal.  The FPGA Business Unit (formerly Actel, with a 35+ year uninterrupted legacy of providing programmable logic solutions) is one of the largest and most profitable BUs inside Microchip. We have revolutionized the FPGA industry with the industry’s most awarded FPGA families - the PolarFire FPGA family and the first RISC-V based PolarFire SoC, delivering class leading power efficiency, reliability and security. With this portfolio, we have enabled commercial applications like the world’s most innovative AI-enabled embedded vision and smart automation products, the world’s most secure and reliable 5G communications networks, as well as the world’s most sophisticated aerospace products that have delivered payloads to Mars and beyond. If you are looking to be a part of a team that is transforming the world of low power compute whilst delivering exceptional top line growth rates, you will be challenged to find a better place to contribute, grow your career and learn to deliver truly remarkable solutions.

 

  • The Candidate will be able to use FPGAs to create systems level designs to bring up and debug use models in the lab.
     
  • Architecture definition and FPGA design creation utilizing all hardware features and IP cores targeted to existing and future Microchip products.
     
  • System and FPGA design must exercise all the use models targeted for each product mimicking end applications in a customer setting.
     
  • Develop high level system and product level validation plans for new and existing silicon products and project, execute per plan. Review dependencies, estimate effort and identify and communicate risk.
     
  • Understand hardware architectures, define use models and execute / oversee system level design implementations required to utilize the silicon features.
     
  • Be an effective contributor in a cross-functional team-oriented environment.
     
  • Write high quality code in Verilog, VHDL and C code. Maintain existing code. Support regression and re-use.
     
  • Learn new system designs and validation methodologies.
     
  • Understand FPGA architectures.
     
  • Collaborate with cross-functional managers/teams to identify and resolve inter-dependencies.
     
  • Define and improve process followed in the department; follow quality metrics and assess per project.
     
  • Must be willing to take late night or early morning calls to interface with engineers working in India Standard Time zone, when and if required.

Job Requirements

Minimum Qualifications:

  1. BS EE/CE with 1+ years of digital FPGA design and validation experience or MS EE/CE with zero+ years of experience.
     
  2. Knowledge of FPGA architectures is a must
     
  3. Possess an understanding of hardware architectures, system level IC design implementation, and knowledge of how to create end use scenarios
     
  4. Design with RTL coding in Verilog or VHDL is a must
     
  5. Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools
     
  6. Technical background in FPGA prototype emulation, and debug
     
  7. Technical background in silicon validation, failure analysis and debug
     
  8. Demonstrate board level debug capabilities in lab environment: hands-on troubleshooting skills for digital logic and analog circuit on PCBs using oscilloscopes, digital analyzers, protocol exercisers and analyzers, FPGA integrated logic analyzers (e.g. Synopsys Identify, Xilinx Chip scope, Altera Signalscope, Lattice Reveal)
     
  9. Good knowledge of validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART, Ethernet, PCI and USB
     
  10. Strong commitment to quality and customer satisfaction
     
  11. Excellent verbal and written communication skills in English
     
  12. Able to travel 0-2 times annually if required

 

Preferred qualifications:

  1. C, C++ or object-oriented programming skills is desirable
     
  2. Knowledge of Linux is desirable
     
  3. Knowledge of U-Boot is desirable
     
  4. Knowledge and experience in embedded firmware development and debug is desirable
     
  5. Knowledge of RISC-V architecture and Instruction Set is desirable
     
  6. Knowledge of PERL/TCL/python scripting is desirable
     
  7. Knowledge and experience in JTAG, SVF and 1532 standards and STAPL programming is desirable
     
  8. Familiarity with any high speed SERDES controllers that make use of 32Gbps PCS, PMA  is a big plus:
    1. PCIe Gen3/4/5
    2. Ethernet 1/10/25/40/100/200G
    3. Interlaken (4.25 to 412.5 Gbps)
    4. OTN OTUx (2.66 to 131 Gbps), or SONET/SDH OC3/12/48/192
    5. (E,X,XGS,NG)-PON or 100G-EPON
    6. Video interfaces SDI-SD/HD/3GHD and SDI (5.94, 11.88Gbps), Displayport (6.48 to 25.92Gbps), HDMI (3.96 to 42.66 Gbps)
    7. JESD204C (6.375 to 32 Gbps)
       
  9. Design and debug experience for any of the below high-speed serial communications protocols is a plus:
    1. Hybrid Memory Cube
    2. CPRI Rate 1 to 10+
    3. Serial Rapid IO 4.1
    4. Firewire
    5. Litefast
    6. USB 3.0
    7. SATA I, II, III
    8. Fiber Channel
    9. CoaXpress
       

Percentage of time spent:

  1. Documentation – 20%
     
  2. Design Creation & Verification – 30%
     
  3. Lab Bringup & Debug – 50%

 

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