Technical Staff Engineer - Validation

San Jose, US

Req ID: 602-22

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Company Description

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.

Job Description

The Candidate will be an expert with Microcontroller based processors and debug interfaces.

  • Architecture definition and FPGA design creation utilizing all hardware features and IP cores targeted to existing and future Microchip products.
  • System and FPGA design must exercise all the use models targeted for each product mimicking end applications in a customer setting.
  • Develop high level system and product level validation plans for new and existing silicon products and project, execute per plan. Review dependencies, estimate effort and identify and communicate risk.
  • Understand hardware architectures, define use models and execute / oversee system level design implementations required to utilize the silicon features.
  • Be not only an effective contributor but also the technical expert related to Microcontroller based processors and debug interfaces in a cross-functional team-oriented environment.
  • Write high quality code in C, Verilog or VHDL. Maintain existing code. Support regression and re-use.
  • Learn new system designs and validation methodologies. Understand FPGA architectures.
  • Act as the authoritative expert in knowledge domain area(s), be able to mentor senior and junior engineers and provide technical guidance.
  • Collaborate with cross-functional managers/teams to identify and resolve inter-dependencies.
  • Define and improve process followed in the department; follow quality metrics and assess per project.
  • Must be willing to take weekly 1-2 late night or early morning calls to interface with the engineering team in India Standard Time zone, when and if required.

Job Requirements

Minimum Qualifications:

  1. BSEE / BSCS or equivalent with 12+ years of experience or MSEE / MSCS with 10+ years of experience.
  2. Must possess knowledge of FPGA or SoC architecture, and their design and debug
  3. Possess an in-depth understanding of hardware architectures, system level IC design implementation, and knowledge of how to create end use scenarios
  4. Strong technical background in SoC prototype emulation, and debug
  5. Strong technical background in silicon validation, failure analysis and debug
  6. Excellent Board level debug capabilities in lab environment: hands-on troubleshooting skills for digital logic and analog circuit on PCB’s using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Identify, Xilinx Chipscope, Altera Signalscope, Lattice Reveal)
  7. Hands-on experience using CPU debug tools such as SoftConsole, EWARM, Keil etc.
  8. Hands-on experience with Program Trace Debug tools such as Lauterbach, Ultradevelop. EWARM, Keil etc.
  9. C, C++ or object-oriented programming skills
  10. Knowledge and experience in developing diagnostic application code (running as bare-metal, on top of RTOS or on top of Linux)
  11. Good understanding of embedded firmware/software development process
  12. Knowledge and experience in JTAG, SVF and 1532 standards and STAPL programming
  13. Good knowledge of validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART, Ethernet, PCI and USB     
  14. Design knowledge with RTL coding in Verilog / VHDL
  15. Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools
  16. Strong commitment to quality and customer satisfaction
  17. Excellent verbal and written communication skills in English
  18. Able to travel 0-2 times annually if required.


Preferred qualifications

  1. Knowledge of developing or debugging U-Boot, Linux kernel is a plus
  2. Knowledge of Linux application profiling is a plus
  3. Familiarity with the bring up and on-board debug of high-speed SERDES is a plus
  4. Hands-on systems level design and debug experience with any one of the following high-speed serial communications protocols (desirable: transaction and upper layers of the OSI protocol; plus to have: PHY, PCS and Data link layer of the OSI protocol stack;):
    1. Aurora
    2. Ethernet 1, 2.5, 5, 10, 25, 40, 50, 100, 200, 400 Gbps, including familiarity with (U)S(X)GMII
    3. USB 3.0
  5. Familiarity with any high speed SERDES controllers that make use of 32Gbps PCS, PMA is a plus:
    1. PCIe Gen3/4/5
    2. Interlaken (4.25 to 412.5 Gbps)
    3. OTN OTUx (2.66 to 131 Gbps), or SONET/SDH OC3/12/48/192
    4. (E,X,XGS,NG)-PON or 100G-EPON
    5. Video interfaces SDI-SD/HD/3GHD and SDI (5.94, 11.88Gbps), Displayport (6.48 to 25.92Gbps), HDMI (3.96 to 42.66 Gbps)
    6. JESD204C (6.375 to 32 Gbps)
  6. Design and debug experience for any of the below high-speed serial communications protocols is a plus, but not necessary:
    1. Hybrid Memory Cube
    2. CPRI Rate 1 to 10+
    3. Serial Rapid IO 4.1
    4. Firewire
    5. Litefast
    6. USB 3.0
    7. SATA I, II, III
    8. Fiber Channel
    9. CoaXpress
  7. Knowledge of PERL/TCL scripting is desirable


Percentage of time spent:

  1. Documentation – 20%
  2. Design Creation & Verification – 30%
  3. Lab Bringup & Debug – 50%


Essential Physical Functions and Working Conditions:

  1. 50 % work in front of computer
  2. 50% work in the lab
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