Senior Technical Staff Engineer-Digital Design

Chandler, US

Req ID: 606-22

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Company Description

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.

Job Description

Senior Technical Staff Design Engineer in IP design group to lead and support the development of modules for use in advanced 32-bit microcontroller and microprocessor product families.

Job Responsibilities:

  • Design IP modules for 32-bit microprocessors and microcontrollers products
  • Guide and support the IP development of multiple team members including regular design reviews and ensuring that quality metrics are met
  • Work with Architecture teams to review IP specifications and objectives. Provide feedback on design feasibility and implementation complexity
  • Generate and maintain Micro Architecture Specification (MAS) at module level and other design flow documentation
  • Work with Verification team to debug and fix issues found in simulation
  • Support the integration of IP modules into SoC products. Provide support for IP related SoC level Verification, Emulation, Silicon debug and ECOs
  • Work with Architecture teams to evaluate IP from external vendors. Liaise with vendors to bring IP in-house for use on SoC products.
  • Define, develop, improve design process flows and methodologies for continuous improvement
  • Work with synthesis/STA engineers to investigate timing concerns at module and SoC level and provide appropriate constraints for use by the BackEnd team
  • Work with DFT engineers to improve test coverage of IP modules
  • Interface with and support cross functional teams such as Applications, Marketing, Analog, CAD and other design organizations
  • Validate and debug silicon products in support of Release to Production

Job Requirements

  • Ability to technically lead and supervise/mentor a team of 4-5 design engineers
  • Must have leadership, mentoring and project management skills to drive and support IP development team
  • Must be able to write reusable System Verilog RTL code, follow design guidelines and best practices
  • Able to write good documentation for micro-architecture specification (MAS) and design flows/methodologies
  • Able to provide clocks and constraints for synthesis and static timing analysis
  • Able to run design quality checks such as Lint, CDC, formal equivalency, power estimation
  • Strong scripting and automation skills.
  • Strong analytical, and problem solving skills, as well as hands-on debugging skills
  • Excellent communication skills. Comfortable presenting in technical forums
  • Knowledge of AXI/AHB interfaces/protocols required.
  • Experience with low power design techniques highly desirable.
  • Understanding of Flash / non-volatile memory-based architectures a plus.
  • Understanding of communication protocols such as Ethernet/1588, USB 2/3, I3C, CAN-FD, and MIPI desirable.
  • Familiarity with System Verilog for verification, UVM, assertion-based verification is desirable
  • Knowledge of Functional Safety standards and associated hardware diagnostics is a plus.
  • Knowledge of graphics controllers and accelerators a plus.
  • Knowledge of motor control peripherals and applications a plus.
  • Experience in analog and mixed signal design a plus (e.g. ADCs, DACs, OPAMPS).
  • Knowledge of audio protocols a plus (e.g. SPDIF, I2S, DSD, TDM)
  • Experience with MS Project and JIRA a plus.
  • Must be able to function in a fast-paced engineering environment that is simultaneously responsible for new IP design and addressing bugs/weaknesses in existing solutions.
  • Must be a team player. Must be able to work effectively with a global team.
  • Must be able to communicate well.
  • MSEE with 12+ years or BSEE with 15+ years of industry experience
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