Engineer Design

Bangalore, IN

Req ID: I695-22

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Company Description

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.

Job Description

 Principal Engineer - SoC Design Lead

WSG group is seeking a Principal Design Engineer willing to carry out IP & chip level design, RTL integration and support functional verification to guarantee functionality for our next generation, mixed signal, Wireless SOC products. Candidate is also expected to have deep understanding of Logic Synthesis, Power Optimization, ECO implementation & Formal Verification with knowledge on Static timing analysis using an Industry leading ASIC Implementation flow. It will require a proactive candidate with a proven record of success in cross functional and cross site team environments.

Key Responsibilities: 

  • Candidate will be responsible for Chip/IP Level Design & RTL integration for SOC
  • Responsible for defining power intent via UPF & develop low-power schemes at Full Chip level
  • Work closely with Functional verification team to ensure correctness of design at SOC/IP Level
  • Responsible for Design Implementation/ECO at Full Chip level
  • Responsible for Low-Power & Design quality checks at Full Chip level

Job Requirements

Required Skills:

  • Expertise in RTL coding using Verilog/System Verilog
  • Knowledge of SOC & IP design flow
  • Knowledge of Low-power Design/Implementation techniques with UPF
  • Familiarity with ECO flows at SOC level
  • Familiarity with Design quality (LINT/CDC)/Low-Power (VC-LP) checks at SOC level
  • Familiarity in Synthesis, Formal Verification, and Static Timing Analysis, preferably with Synopsys tools
  • Excellent debug skills in both Functional and Gate level simulations
  • Knowledge of revision control tools such as CVS, ICManage, Perforce, Git
  • Knowledge of common UNIX scripting languages (Perl, Python, csh, etc.) & C Programming Language
  • Superior Written and Verbal Communication skill
  • Experience working with cross functional global teams
  • Clear history of task ownership and proactively addressing issues


Desired Skills:

  • Experience with MIPS/ARM Processor based subsystem
  • Experience with Verification Methodologies such as UVM/VMM
  • Familiarity with DFT and Backend implementation flows
  • Knowledge and exposure to complete SOC RTL to GDS to silicon release flow
  • Experience working on Wi-Fi, WLAN, or Bluetooth products
  • Good Knowledge of Subsystems like Security/Touch Interface/JTAG/ADC


Required Education:

  • BS or MS in Electrical/Electronic Engineering with 8+ years of experience, MSEE preferred
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